CWE Reference

CWE for vhdl

Browse cwe for vhdl with official CWE context and Glexia analysis.

Release 4.20listing

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Showing 14 of 14 CWE records.

CWE-327WeaknessClass

CWE-327: Use of a Broken or Risky Cryptographic Algorithm

The product uses a broken or risky cryptographic algorithm or protocol.

Not Language-Specific Undetermined Verilog VHDL Architecture and Design Implementation Architecture and Design

CWE-1221WeaknessBase

CWE-1221: Incorrect Register Defaults or Module Parameters

Hardware description language code incorrectly defines register defaults or hardware Intellectual Property (IP) parameters to insecure values.

Verilog VHDL Architecture and Design Implementation

CWE-1223WeaknessBase

CWE-1223: Race Condition for Write-Once Attributes

A write-once register in hardware design is programmable by an untrusted software component earlier than the trusted software component, resulting in a race condition issue.

Verilog VHDL Architecture and Design

CWE-1224WeaknessBase

CWE-1224: Improper Restriction of Write-Once Bit Fields

The hardware design control register "sticky bits" or write-once bit fields are improperly implemented, such that they can be reprogrammed by software.

Verilog VHDL Architecture and Design

CWE-1251WeaknessBase

CWE-1251: Mirrored Regions with Different Values

The product's architecture mirrors regions without ensuring that their contents always stay in sync.

VHDL Verilog Architecture and Design

CWE-1269WeaknessBase

CWE-1269: Product Released in Non-Release Configuration

The product released to market is released in pre-production or manufacturing configuration.

VHDL Verilog Compiled Undetermined Implementation Integration Manufacturing

CWE-1272WeaknessBase

CWE-1272: Sensitive Information Uncleared Before Debug/Power State Transition

The product performs a power or debug state transition, but it does not clear sensitive information that should no longer be accessible due to changes to information access restrictions.

VHDL Verilog Hardware Description Language Undetermined Architecture and Design Implementation

CWE-1273WeaknessBase

CWE-1273: Device Unlock Credential Sharing

The credentials necessary for unlocking a device are shared across multiple parties and may expose sensitive information.

VHDL Verilog Compiled Undetermined Integration Manufacturing

CWE-1279WeaknessBase

CWE-1279: Cryptographic Operations are run Before Supporting Units are Ready

Performing cryptographic operations without ensuring that the supporting inputs are ready to supply valid data may compromise the cryptographic result.

Verilog VHDL Not Language-Specific Undetermined Architecture and Design Implementation

CWE-1280WeaknessBase

CWE-1280: Access Control Check Implemented After Asset is Accessed

A product's hardware-based access control check occurs after the asset has been accessed.

Verilog VHDL Not Language-Specific Undetermined Implementation

CWE-1296WeaknessBase

CWE-1296: Incorrect Chaining or Granularity of Debug Components

The product's debug components contain incorrect chaining or granularity of debug components.

Verilog VHDL Not Language-Specific Undetermined Implementation

CWE-1297WeaknessBase

CWE-1297: Unprotected Confidential Information on Device is Accessible by OSAT Vendors

The product does not adequately protect confidential information on the device from being accessed by Outsourced Semiconductor Assembly and Test (OSAT) vendors.

Verilog VHDL Not Language-Specific Undetermined Architecture and Design

CWE-1298WeaknessBase

CWE-1298: Hardware Logic Contains Race Conditions

A race condition in the hardware logic results in undermining security guarantees of the system.

Verilog VHDL Architecture and Design Implementation

CWE-1311WeaknessBase

CWE-1311: Improper Translation of Security Attributes by Fabric Bridge

The bridge incorrectly translates security attributes from either trusted to untrusted or from untrusted to trusted when converting from one fabric protocol to another.

Verilog VHDL Architecture and Design Implementation