Security readout for executives and security teams
Plain-English summary
A discrepancy between the intended OR1200 hardware design and its synthesized netlist can cause the processor to behave unexpectedly. The record assigns a critical 9.1 score because confidentiality and availability could be severely affected, but it does not identify specific deployed products or confirm real-world exploitation.
Executive priority
Treat this as a high-priority investigation where OR1200-derived hardware is deployed in sensitive or exposed systems. Do not assume fleet-wide impact from the score alone: first establish whether commit 83ac6b entered production designs, then prioritize verification based on system criticality and network exposure.
Technical view
CVE-2025-51679 concerns openRISC OR1200 commit 83ac6b and is classified as CWE-1281. The reported weakness is an RTL-to-netlist mismatch, meaning synthesized hardware may not preserve the source design’s behavior. The CVSS vector indicates network reachability, low complexity, no privileges or interaction, high confidentiality and availability impact, and no integrity impact.
Likely exposure
Exposure is most plausible in FPGA, ASIC, research, or embedded implementations derived from the identified OR1200 commit. The CVE record provides no vendor, product, version, CPE, or deployment inventory data, so exposure cannot be determined from ordinary vulnerability scanners alone.
Exploitation context
The source bundle provides no evidence of active exploitation, and the CVE is not listed as KEV. Although the CVSS vector describes remote, unauthenticated reachability, the available description does not explain the necessary system configuration, trigger conditions, or practical attack path.
Researcher notes
The public record is unusually sparse: affected vendor, product, and versions are recorded as unavailable. It references an OR1200 commit while linking a mor1kx issue, so project scope and lineage require careful confirmation. No patch, fixed commit, affected synthesis tools, trigger details, or exploitation evidence is established in the supplied material.
Mitigation direction
- Inventory hardware designs and firmware platforms derived from OR1200 commit 83ac6b.
- Check the OpenRISC issue and project guidance for confirmed corrections or replacement commits.
- Re-synthesize affected designs using validated sources after maintainers identify an approved correction.
- Apply compensating isolation to potentially affected systems until their synthesized behavior is verified.
Validation and detection
- Record the exact source commit, synthesis toolchain, settings, and generated netlist for each implementation.
- Compare RTL behavior with gate-level or netlist simulation across security-relevant states.
- Review synthesis logs and equivalence-checking results for unexplained behavioral differences.
- Confirm any proposed correction against maintainer guidance and repeat regression testing.
Public sources used
Generated from the cited source records. This long-tail analysis has not been individually reviewed by a named human.
Conservative CVE-to-ATT&CK context
These mappings and lookup hints may be relevant to the vulnerability behavior, CWE, affected product, or exposure path. Glexia-inferred context is not an official MITRE, ATT&CK, CWE, or CVE Program mapping.
ATT&CK lookup starting points
Use these exact CWE pages and searches to review the Glexia ATT&CK library from this CVE's weakness and description context.
CWE-1281: Exact CWE lookup
Use the exact CWE identifier as the starting point before reviewing related ATT&CK behavior. Open the exact CWE lookup page first, then review the ATT&CK searches from that MITRE weakness context. This is a Glexia lookup hint, not an official ATT&CK mapping.
Open ATT&CK lookupCVE-2025-51679 mapping review
Open the CVE-to-ATT&CK bridge for reviewed, inferred, or future official mappings tied to this CVE.
Open ATT&CK lookup- Severity
- Critical
- CVSS
- 9.1 (3.1)
- Known Exploited
- No
- Published
Vector: CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
CNA and ADP enrichment extracted from CVE v5
These fields come from the CVE record and ADP containers, not from Glexia's Take. They preserve time-varying source decisions such as CISA SSVC, KEV status, CVSS metrics, and provider references.
SSVC decision data
CVSS vector scores
1 official scoreWe collect every scored CVSS vector available in the official CNA and ADP containers. When more than one version is present, the table keeps the source vectors side by side instead of collapsing them into the highest score.
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H3.95.2CISA-ADPVulnerability scoring details
Base CVSS 3.1 score
9.1CriticalVector: CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H
Vulnerability timeline
Timeline events are normalized from CVE metadata, CNA source timelines, ADP timelines, and KEV metadata when present.
- CVE reservedCVE Program
The CVE ID was reserved by the assigning CNA.
- CVE publishedCVE Program
The CVE record was published.
- CVE updatedCVE Program
The CVE record metadata indicates this as the latest update time.
ADP provider summaries
Source materials
- CVE List V5 sourceCVE List V5
- https://github.com/openrisc/mor1kx/issues/161CVE reference, mitre
- https://www.arxiv.org/abs/2504.18812CVE reference, mitre
- https://mason.gmu.edu/~rsaravan/projects/synfuzz/cve/cve.htmlCVE reference, mitre
Products and packages named in the record
CWE details
CWE links open Glexia weakness intelligence pages with official CWE context, developer remediation guidance, and related CVE mappings.
Sequence of Processor Instructions Leads to Unexpected Behavior
Sequence of Processor Instructions Leads to Unexpected Behavior represents a recurring weakness pattern that can create exploitable paths when design, validation, or implementation controls are missing.