CVE-2025-51677: An issue was discovered in openRISC OR1200 commit 83ac6b.
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior.
Security readout for executives and security teams
Plain-English summary
CVE-2025-51677 describes a mismatch between the intended OR1200 CPU RTL and a synthesized netlist at an output port. Hardware built from the affected design could behave differently than expected, creating integrity and availability risk. Public data does not identify packaged products, deployed devices, or a vendor patch.
Executive priority
Treat as high priority only if your organization uses OR1200-derived hardware IP. For most software-only environments, immediate exposure is likely low, but hardware teams should verify provenance promptly.
Technical view
The record ties the issue to openRISC OR1200 commit 83ac6b and reports an RTL-versus-netlist output mismatch. The CVSS 3.1 score is 9.1, with high integrity and availability impact and no confidentiality impact. Affected CPEs and versions are listed as n/a, so exposure must be assessed from design provenance.
Likely exposure
Likely exposure is limited to organizations using, evaluating, or deriving hardware from OR1200 commit 83ac6b or related generated netlists. Evidence does not show broad consumer software exposure or named downstream products.
Exploitation context
The bundle reports KEV as false and provides no cited evidence of active exploitation. The risk is design-level: a mismatch may cause incorrect CPU output behavior after synthesis, which can affect system correctness or reliability.
Researcher notes
Public evidence is thin: the record names a commit and mismatch class but not a fixed version, exploit path, or affected products. Avoid assuming internet exploitability despite the CVSS vector; validate against hardware design flows and upstream issue details.
Mitigation direction
Check upstream OpenRISC issue and CVE pages for vendor guidance or corrected commits.
Inventory FPGA, ASIC, and verification projects using OR1200 commit 83ac6b.
Avoid promoting affected netlists into production until equivalence is verified.
Run RTL-to-netlist equivalence and regression checks for OR1200 output behavior.
Document any downstream products or builds derived from the affected commit.
Validation and detection
Confirm whether OR1200 commit 83ac6b exists in your hardware source history.
Compare synthesized netlists against trusted RTL for relevant CPU output ports.
Review synthesis logs and verification artifacts for output mismatch evidence.
Check whether downstream forks incorporated fixes after the referenced issue.
Track CVE record updates for clarified affected versions or remediation.
Generated from the cited source records. This long-tail analysis has not been individually reviewed by a named human.
Potential ATT&CK relevance
Conservative CVE-to-ATT&CK context
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ATT&CK lookup starting points
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cwe · medium confidence lookup
CWE-116: User-session and phishing behavior lookup
Client-side and session-facing weaknesses should be reviewed alongside initial-access and user-execution behaviors. Open the exact CWE lookup page first, then review the ATT&CK searches from that MITRE weakness context. This is a Glexia lookup hint, not an official ATT&CK mapping.
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CWE links open Glexia weakness intelligence pages with official CWE context, developer remediation guidance, and related CVE mappings.
CWE-116 · source CWE mapping
Improper Encoding or Escaping of Output
Improper Encoding or Escaping of Output represents a recurring weakness pattern that can create exploitable paths when design, validation, or implementation controls are missing.