CVE-2024-42279: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
In the Linux kernel, the following vulnerability has been resolved:
spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer
While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.
Security readout for executives and security teams
Plain-English summary
A flaw in Linux’s Microchip CoreSPI driver can leave old data in hardware buffers. A later SPI operation may receive those stale bytes as if they were new, potentially corrupting data or exposing prior transfer contents. Exposure is limited to systems using the affected SPI controller and driver; it is not a general vulnerability in every Linux system.
Executive priority
Treat this as a high-priority targeted remediation for products using Microchip CoreSPI, especially where SPI data influences safety, secrets, or device control. Do not treat it as a fleet-wide Linux emergency without confirming the affected hardware and driver. Escalate ambiguous vendor version mappings for prompt confirmation.
Technical view
When a transfer has no receive buffer, the interrupt handler does not drain the RX FIFO. A subsequent transfer can copy residual bytes into the beginning of its receive buffer. The correction clears both RX and TX FIFOs before every transfer. The supplied CVSS 3.1 assessment is 7.8 with local, low-privileged access and potential confidentiality, integrity, and availability impact.
Likely exposure
Likely exposure is concentrated in embedded systems, appliances, or boards using Linux with the Microchip CoreSPI controller. The supplied affected-version data is ambiguous and includes commit identifiers alongside kernel versions, so determine exposure through hardware inventory, driver usage, vendor guidance, and comparison with the referenced stable fixes.
Exploitation context
The bundle does not establish active exploitation, and the CVE is not listed as KEV. The CVSS vector indicates local, low-privileged access rather than remote exploitation. Practical abuse would likely require an attacker to influence affected SPI transfers; the sources do not document a public exploit or confirmed attack path.
Researcher notes
The stated failure mode is stale FIFO data crossing transfer boundaries. Security consequences depend on what the SPI bus carries and whether an attacker can initiate or shape transfers. The source bundle provides three stable-kernel corrections but no clear fixed-version table, exploit evidence, CWE assignment, or demonstrated impact scenario; avoid inferring more specific reachability.
Mitigation direction
Update to a vendor-supported kernel containing the applicable referenced stable fix.
Prioritize embedded and appliance systems that actively use the Microchip CoreSPI driver.
Consult device or distribution vendors for corrected package versions and deployment guidance.
Restrict untrusted local access to interfaces or services capable of initiating relevant SPI transfers.
Validation and detection
Identify devices using the Microchip CoreSPI controller and corresponding Linux driver.
Compare deployed kernel code or vendor packages against the referenced stable fixes.
Verify the corrected driver clears RX and TX FIFOs before each transfer.
After updating, test consecutive transmit-only and receive transfers for stale leading data.
Generated from the cited source records. This long-tail analysis has not been individually reviewed by a named human.
Potential ATT&CK relevance
Conservative CVE-to-ATT&CK context
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CVE-2024-42279 mapping review
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