CVE-2017-13093: The P1735 IEEE standard describes flawed methods for encrypting electronic-design intellectual property (IP), including modification of encrypted IP cyphertext to insert hardware trojans

Security readout for executives and security teams

IEEE P1735 encryption for electronic-design IP used flawed methods. Organizations relying on P1735-protected chip or FPGA design IP could face intellectual property disclosure or malicious modification risks, including hardware trojan insertion. The supplied sources do not identify active exploitation or specific fixed vendor versions. Exposure is most likely in semiconductor, FPGA, SoC, and EDA workflows that exchange or consume encrypted third-party IP using IEEE P1735. The bundle names the IEEE P1735 standard, not specific products or versions. Treat this as a high-priority supply-chain and IP-protection risk if the organization designs, licenses, or consumes encrypted electronic-design IP. Priority is lower for organizations with no semiconductor, FPGA, or EDA dependency. Mitigation focus: Inventory workflows and tools that use IEEE P1735 encrypted IP.; Check EDA vendor advisories for affected implementations and corrected versions.; Request supplier attestations for encrypted IP provenance and P1735 handling..

Prepared

Jun 7, 2026, 13:02 UTC (UTC+00:00)

Generated from the cited source records. This long-tail analysis has not been individually reviewed by a named human.