CWE-1293: Missing Source Correlation of Multiple Independent Data
The product relies on one source of data, preventing the ability to detect if an adversary has compromised a data source.
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The product relies on one source of data, preventing the ability to detect if an adversary has compromised a data source.
The lack of protections on alternate paths to access control-protected assets (such as unprotected shadow registers and other external facing unguarded interfaces) allows an attacker to bypass existing protections to the asset that are only performed against the primary path.
Hardware structures shared across execution contexts (e.g., caches and branch predictors) can violate the expected architecture isolation between contexts.
The product contains a component that cannot be updated or patched in order to remove vulnerabilities or significant bugs.
The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.
The product is built from multiple separate components, but it uses a component that is not sufficiently trusted to meet expectations for security, reliability, updateability, and maintainability.
The product does not properly handle unexpected physical or environmental conditions that occur naturally or are artificially induced.
The product uses default credentials (such as passwords or cryptographic keys) for potentially critical functionality.
The product uses default passwords for potentially critical functionality.
The product uses a default cryptographic key for potentially critical functionality.
The product has a dependency on a third-party component that contains one or more known vulnerabilities.
A processor event or prediction may allow incorrect operations (or correct operations with incorrect data) to execute transiently, potentially exposing data over a covert channel.
A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.
A processor event or prediction may allow incorrect or stale data to be forwarded to transient operations, potentially exposing data over a covert channel.
Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.